The present invention refers to a transition mode operating device for the correction of the power factor in switching power supply units.
These devices are generally used for the active correction of the power factor (PFC) for switching power supply units used in common electronic appliances such as computers, televisions, monitors, etc and to power fluorescent lamps, in other words pre-regulation stages with forced switching which have the task of absorbing from the network supply a current that is virtually sinusoidal and is in phase with the network voltage. A switching power supply unit of the present type therefore comprises a PFC and a DC-DC converter connected to the PFC output.
A switching power supply unit of the typical type comprises a DC-DC converter and an input stage connected to the electric energy distribution network, consisting of a full-wave diode rectifier bridge and of a capacitor connected immediately downstream so as to produce a non-regulated direct voltage from the network alternating sinusoidal current. The capacitor has sufficiently large capacitance because at the terminals thereof the AC signal is relatively small compared with the DC level. The bridge rectifier diodes therefore conduct only a small portion of each half cycle of the network voltage because the momentary value of the network voltage is lower than the voltage on the capacitor for most of the cycle. The current absorbed by the network is accordingly a series of narrow pulses the amplitude of which is 5 to 10 times the resulting average value.
This has considerable consequences: the current absorbed from the line has peak and effective values that are much greater than in case of the absorption of sinusoidal current, the network voltage is distorted by the almost simultaneous pulsed absorption of all the appliances connected to the network, in the case of three-phase systems the current in the neutral conductor is greatly increased, and the energy potential of the system for producing electric energy is poorly used. In fact, the wave shape of a pulsed current is very rich in odd harmonic distortions that, while not contributing to the power returned to the load, contribute to increasing the effective current absorbed by the network and therefore to increasing the dissipation of energy.
In quantitative terms this can be expressed both in terms of power factor (PF), defined as the ratio between real power (the power that the power supply unit returns to the load plus the power dissipated inside it in the form of heat) and apparent power (the product of the effective network voltage for the effective absorbed current), and in terms of total harmonic distortion (THD), generally defined as the percentage ratio between energy associated with all the harmonic distortions of a superior order and that associated with the fundamental harmonic distortion. Typically, a power supply unit with a capacitive filter has a PF between 0.4-0.6 and a THD greater than 100%.
A PFC arranged between the rectifier bridge and the input of the DC-DC converter enables an almost sinusoidal current, which is in phase with the voltage, to be absorbed from the network and brings PF close to one and reduces THD.
The PFCs generally comprise a converter provided with a power transistor and an inductor coupled to it and a control device coupled to the converter in such a way as to obtain from a network alternating input voltage a direct voltage regulated at the output. The control device is capable of determining the on time period Ton and the off time period Toff of the power transistor; the total of the period of Ton and the period of Toff time gives the cycle period or switching period of the power transistor.
The commercially available PFC circuit types are basically of two kinds that differ according to the different control technique used: pulse width modulation (PWM) control with fixed frequency wherein current is conducted continuously into an inductor of the power supply unit and a variable frequency PWM control, also known as ‘transition mode’ (TM) because the inductor current is reset exactly at the end of each switching period. TM control can be operated both by controlling inductor current directly or by controlling the time period Ton. The fixed-frequency control technique provides better performance but uses complex circuit structure whereas TM technique requires a more simple circuit structure. The first technique is generally used with high power levels whilst the second technique is used with medium—low power levels, normally below 200 W.
A PFC pre-regulatory stage of the TM type which comprises a boost converter 20 and a control device 1 is schematically shown in FIG. 1. The boost converter 20 comprises a full-wave diode rectifier bridge 2 with a input network voltage Vin, a capacitor C1 (that is used as a high-frequency filter) with a terminal connected to the diode bridge 2 and the other terminal connected to ground, an inductor L connected to a terminal of the capacitor C1, a MOS power transistor M with the drain terminal connected to a terminal of the inductor L downstream of the latter and having the source terminal connected to a resistance Rs connected to ground, a diode D having the anode connected to the common terminal of the inductor L and the transistor M and the cathode connected to a capacitor Co, having the other terminal connected to ground. The boost converter 20 generates a direct output voltage Vout on the capacitor Co that is greater than the network maximum peak voltage, typically 400 V for systems powered by European network supplies or by a universal supply. Said output voltage Vout is the input voltage of the DC-DC converter connected to the PFC.
The control device 1 has to maintain the output voltage Vout at a constant value by feedback control. The control device 1 comprises an error amplifier 3 suitable for comparing part of the output voltage Vout, in other words the voltage Vr deriving from Vr=R2×Vout/(R2+R1) (where resistances R1 and R2 are connected in series and said series is parallel to the capacitor Co) with a reference voltage Vref, for example 2.5V, and generates an error signal proportional to their difference. The frequency of output voltage Vout is twice that of the network voltage and is superimposed on the direct value. However, if the band amplitude of the error amplifier is significantly reduced (typically to below 20 Hz) by means of a suitable compensation network comprising at least one capacitor and assuming an almost stationary condition operation, in other words with constant effective input voltage and constant output load, the AC component of the output voltage will be greatly attenuated and the error signal will become constant.
The error signal Se is sent to a multiplier 4, where it is multiplied by a signal V1 given by part of the network voltage rectified by the diode bridge 2. At the output of the multiplier 4 there is a signal Sm provided by a rectified sinusoidal current, the amplitude of which obviously depends on the effective network voltage and on the error signal.
The signal Sm is sent to the non-inverting input of a PWM comparator 5 whereas the signal Srs present on the resistance Rs persists on the inverting input. If the signals Srs and Sm are equal, the comparator 5 sends a signal to a control block 6 that drives the transistor M, which in this case switches it off. In this way the output signal Sm of the multiplier determines the peak current of the transistor M and this is then enveloped by a rectified sinusoid.
After the MOS has been switched off the inductor L discharges the energy stored in it onto the load until it is completely emptied. At this point, the diode D does not allow the current to flow and the drain terminal of the transistor MOS continues to float, so that its voltage moves towards the momentary input voltage through resonance oscillations between the parasitic capacitance of the terminal and the inductance of the inductor L. The drain voltage is thus rapidly reduced, said drain voltage being coupled to a terminal to which a zero current detector block 7, which belongs to the block 6, is connected by means of an auxiliary winding of the inductor. This block 7 identifies this negative front, sends a pulsed signal to an OR gate 8, the other input of which is connected to a starter 10 that is suitable for sending a signal to the OR gate 8 at the instant of start time; the output signal S of the OR gate 8 is the set input S of a set-reset flip-flop 11 having another input R that is the output signal of the device 5, it having an output signal Q. The signal Q is sent to the input of a driver 12, which controls the turning on and off of the transistor M.
The control device needs to form the sinusoidal reference for the current and this is performed by means of a resistive divider arranged to the input of the converter; in this way a part of the rectified network voltage is made available to the control device.
However the use of said resistive divider increases the component count of the circuit in the whole and it increases the power dissipation of the same circuit.
PFCs without elements for reading the rectified network voltage belong to the state of the art as the PFC shown in FIG. 2 which is a PFC operating in transition mode with constant turning on time Ton; the elements equal to the PFC in FIG. 1 are represented by the same references and only the differences as regards the PFC in FIG. 1 which refer to the elements and the managing thereof are shown hereinafter.
If it is assumed that the current absorbed by the network from the PFC in almost stationary running conditions (in order words with constant effective input voltage and constant output load) is sinusoidal in each switch-on cycle of the transistor M, the peak current of the inductor L is Ip=Vin×Ton/L, Ton being the time period during which the transistor M is switched on. As the input voltage is sinusoidal, if Ton is kept constant during each network cycle, the peak current of the inductor L is enveloped by a sinusoidal current. An appropriate filter between the network and the input of the rectifier bridge (always present for questions of electromagnetic compatibility) filters the input current, eliminating the high-frequency components, so that the current absorbed from the network is a sinusoidal current of the same frequency and in phase with the network current.
Normally, in PFCs of the TM type controlled in peak-current mode the constancy of switch-on time Ton is a result of forcing the peak current of the inductor to follow a sinusoidal reference. This reference is taken from the rectified voltage after the bridge the amplitude of which is corrected with the error signal coming from the regulating loop of the output voltage, by means of a multiplier block. The constant Ton approach has the advantage that it does not require reading of the input voltage or of a multiplier block.
The error signal Se generated by the error amplifier 3 having a compensation capacitor Ccomp in such case is sent to the inverting input of a PWM comparator 5 whereas at the non-inverting input a ramp signal Sslope persists, which signal is generated by a current generator Ic connected to a VDD supply, a capacitor C and a switch SW. If the signals Se and Sslope are the same the comparator 5 sends a signal to a control block 6 suitable for driving the transistor M, which in this case switches it off. As the error amplifier output is constant the duration of the conduction period of the transistor MOS M is constant within each network cycle. As the load and/or the network voltage conditions vary the error signal changes and sets the Ton value required to regulate the output voltage. As soon as the transistor MOS is switched off SW is closed and C is discharged.
After the transistor MOS is switched off the inductor L discharges the energy stored on the load until it is completely emptied. At this point the diode D does not permit the conduction of current and the drain terminal of the transistor M remains floating, so that its voltage Vdrain moves towards the momentary input voltage by means of resonance oscillations between the parasitic capacity of the terminal and the inductance of the inductor L. The drain voltage Vdrain therefore falls rapidly, being coupled by an auxiliary coil of the inductor L with the terminal to which a zero current detector block 7 is connected which is part of the block 6. This block 7 identifies this negative front, sends a pulsed signal to an OR gate 8, the other input of which is connected to a starter 10 that is suitable for sending a signal to the OR gate 8 at the instant of start time; the output signal S of the gate 8 OR is the set input S of a set-reset flip-flop 11 with another input R that is the output signal to the device 5, it having two output signals, Q and P (the negated Q signal). The signal Q is sent to the input of a driver 12, which in this case commands the renewed switch-on of the transistor M (in other cases it can command it to be switched off), and the signal P in this case commands the opening of the switch SW (in other cases it commands it to be closed) in such a way that the capacitor C can recharge, thereby starting a new switching cycle. In this way the PFC works in transition mode.
The PFC shown in FIG. 2 does not have resistive elements adapted to obtain the reading of the rectified network voltage, however the particular of the approach with constant time period Ton allows its use in appliances with small variations of the network voltage and of the load. In fact if for the PFC in FIG. 1 the input voltage Vin can vary from 88 VAC to 264 VAC and the variation of the output power Pout is between the 1% and the 100% of the output power with a nominal load, for the PFC in FIG. 2 the input voltage Vin can vary of the 20% and the variation of the output power Pout is between the 30% and the 100% of the output power with a nominal load.
In view of the state of the technique described, the object of the present invention is to provide a transition mode operating device for the correction of the power factor in switching power supply units which is usable for a very large range of the input voltage and a very large range of the load.